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the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. not all devices/types available in every country. please check with local nec representative for availability and additional information. mos integrated circuit m m m m pd63711 compact disc digital servo/data processor with on-chip rf amplifier document no. s14470ej1v1pm00 (1st edition) date published november 1999 n cp(k) printed in japan preliminary product information the m pd63711 is an lsi that has all of the functions required to control a cd player, with a digital servo, data processor, rf amplifier, audio dac, and post-processing filter incorporated on a single chip. cd-text is also supported. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. m m m m pd63711 users manual: to be prepared features ? realization of set miniaturization by integrating a digital servo, data processor, 8-fs oversampling digital filter, d/a converter, and rf amplifier on a single chip. ? on-chip scf (switched capacitor filter) as audio dac block post-processing filter ? employment of digital loop filter for four servo systems. since the filter coefficient is programmable, a variety of characteristics can be realized. ? on-chip automatic adjustment function. automatic adjustments of focus offset, focus gain, focus balance, tracking offset, tracking gain, and tracking balance are possible. ? on-chip 16-kbit sram needed for de-interleaving. ? since a digital pll circuit is employed, the external components of the bit clock regeneration circuit are not needed. ? circ error correction capability c1: double correction c2: quadruple correction (cd-rom mode) ? on-chip fourth order d s type one-bit d/a converter and post-processing filter ? on-chip mirror circuit, defect circuit, rfok circuit, and efm comparator. ? a de-emphasis circuit can be controlled via a microcontroller for supporting connection with shock-proof ics. ? crystal oscillation stop function ? pickup of both current and voltage output can be supported. ? single 5-v power supply ordering information part number package m pd63711gc-8eu 100-pin plastic lqfp (fine pitch) (14 14 mm)
preliminary product information s14470ej1v1pm00 2 m m m m pd63711 pin configuration (top view) ? 100-pin plastic lqfp (fine pitch) (14 14 mm) m m m m pd63711gc-8eu d.gnd rfok rst a0 stb sck so si xtalen d.v dd da.v dd rout da.gnd regc da.gnd lout da.v dd r+ r - l - l+ x.v dd xtal xtal x.gnd d.v dd emph flag din dout sckin scko lrckin lrck hold/wdck tx d.gnd c16m limit d.v dd lock rfck mirr/wfck plck d.gnd c1d1 c1d2 c2d1 c2d2 c2d3 a.v dd pn ld pd a.gnd tec te2 teo te - feo fe - refout a.v e f d b c a a.gnd rf - eq1 eq2 rfo agci agco rfi c3t asy efm a.v dd dac3 dac2 dac1 dac0 md sd td fd a.gnd atest test1 test0 d.gnd tstb tsck tsi tso pack d.v dd 80 100 90 50 40 30 60 70 10 1 20
preliminary product information s14470ej1v1pm00 3 m m m m pd63711 a, c, b, d, f, e: error signal input plck: pll lock a.gnd: analog ground pn: apc circuit polarity control a.v dd: analog power supply limit: pick inner detect a0: address 0 r+, rC: r-channel sound data output (pwm) agci: agc amp input refout: reference output agco: agc amp output regc: capacitor connection for regulator asy: slice level rfC: impedance connection to rf amp for atest: analog test negative feedback c16m: clock 16 mhz rfck: read frame clock c1d1, c1d2,: correction data rfi: rf signal input c2d1 to c2d3 rfo: rf amp output c3t: capacitance connection for 3t signal rfok: rfok signal detecting circuit rout: r-channel audio signal output d.gnd: digital ground rst: reset d.v dd: digital power supply sck: serial clock da.gnd: d/a converter ground sckin: serial clock input da.v dd: d/a converter power supply scko: serial clock output dac0 to dac3: d/a converter output sd: sled drive din: data input si: serial data input dout: data output so: serial data output efm: efm signal stb: strobe emph: emphasis td: tracking drive eq1, eq2: equalizer parts connection for rf amp te: tracking error fd: focus drive teC: impedance connection to tracking fe: focus error error amp for negative feedback feC: impedance connection to focus error te2: tracking error amp output multiplied amp for negative feedback by two feo: focus error amp output tec: tracking error comparator flag: flag teo: tracking error amp output hold/wdck: hold control/word clock test0, l+, lC: l-channel sound data output (pwm) test1: test ld: laser diode control current output tsck: serial clock for text data lock: lock tsi: parameter input for text data lout: l-channel audio signal output tso: serial text data output lrck: lr clock tstb: text parameter strobe lrckin: lr clock input tx: transmit data md: motor drive x.gnd: crystal oscillator ground mirr/wfck: mirr signal/write frame clock x.v dd: crystal oscillator power supply pack: pack signal sync xtal, xtal: crystal connection pd: photo diode signal (for detecting xtalen: crystal oscillation enable laser power) input
preliminary product information s14470ej1v1pm00 4 m m m m pd63711 block diagram defect comparator mirenv c2d3 c2d2 c2d1 c1d2 c1d1 d.gnd plck mirr/wfck rfck lock dout din flag emph d.v dd d.v dd limit c16m d.gnd tx hold /wdck lrck lrckin scko sckin agci rfo eq2 eq1 rf - a.gnd pd ld pn a.v dd f e a.v dd refout fe - feo te - teo te2 tec a.gnd a c b d xtal xtal da.gnd da.gnd da.v dd x.gnd x.v dd da.v dd l+ rout d.v dd l - r - r+ lout tsck tsi tso pac k d.v dd a.v dd dac3 dac2 dac1 dac 0 md sd td fd a.gnd atest test 0 d.gnd tstb agco rfi c3t asy efm output processor error correction processor efm comparator efm rf amplifier block fok mirr defect feo teo a3t focus register tracking register subcode processor 8 over-sampling digital filter d/a interface circuit output buffer auto gain control microcontroller interface de-emphasis circuit osc digital audio interface digital pll clv processor fd/td/sd/md control memory processor timing generator efm demodulator 16 k sram microcontroller interface cd-text decoder d.gnd rst rfok si so sck stb a0 output buffer noise shaver switch multi- plier svrom adder rom decoder svcram svdram feofs teofs compa- rator rfenv a/d converter d/a fok xtalen regc test1 scf defect efm noise shaver
preliminary product information s14470ej1v1pm00 5 m m m m pd63711 rf amplifier block remark the unit of resistance is w and capacitance is f. mirr fok pn pd vreg lds apn 16 k 1 k 150 k 100 k 100 k 110 k 1 k ld 27 p te - teo 20 k or 30 k a/d 48 k 48 k 80 k 110 k te2 60 k f e 56 p 8 k to 16 k to 32 k 5 ways 80 k 10 k, 20 k 10 k, 20 k 48 k 48 k fe - feo a c b d efm asy rfi 40 k 15 k 39 k 2 k 0.01 40 k 40 k 40 k 75 k 10 k 0.01 0.1 + - defect a3t 0.1 eq setting: select eq1 or eq2 according to the sw2 bit of the 39h command 5.6 k to 12 k to 24 k 16 ways agco rf - eq1 eq2 rfo agci 10 k 10 k 10 k 2.5 v 4 p peak detection detection current 7-level switching s/h lpf c3t vref vref vref vref + - + - bottom detection + - + - + - + - vref + - vref + - vref + - vref + - vref + - vref + - vref vref vref + - + - + - a/d + - + - 40 k 40 k 1 p + - 30 k 20 k 20 k 20 k 50 k to 200 k to 480 k 7 ways 50 k to 200 k to 480 k 7 ways vref 6 k to 10 k to 16 k 5 ways 5 k, 10 k 2 ways 3 p 3 p 110 k d/a efm 0.1 28 k to 58 k to 118 k 7 ways d/a 28 k to 58 k to 118 k 7 ways 5 k 5 k 80 k 288 k to 224 k to 160 k 128 ways 110 k 112 k, 56 k, 28 k 3 ways detection current 7-level switching 7 ways 112 k, 56 k, 28 k 3 ways 40 k 40 k m m m m m
preliminary product information s14470ej1v1pm00 6 m m m m pd63711 contents 1. pin functions ............................................................................................................ ........................ 7 2. digital filter flowcharts ............................................................................................... ....... 12 3. microcontroller interface commands............................................................................ 16 3.1 servo system commands .................................................................................................... ...... 16 3.2 rf system commands ....................................................................................................... ........ 30 3.3 signal processing system commands ..................................................................................... 41 3.4 cd-text function......................................................................................................... .............. 54 3.5 status................................................................................................................... ......................... 57 4. package drawing.......................................................................................................... ................ 58 5. recommended soldering conditions .................................................................................. 59
preliminary product information s14470ej1v1pm00 7 m m m m pd63711 1. pin functions pin no. pin name description i/o initial value 1 d.gnd logic circuit gnd C C 2 rfok rfok signal output pin o undefined 3 rst reset signal input pin (active low) i C 4 a0 command/parameter identifying signal input pin this is used in combination with stb. a0 = l: with stb active, set to address register a0 = h: with stb active, parameter setting iC 5 stb data strobe signal input pin this is the signal for latching serial data inside the lsi. iC 6 sck clock signal input pin for serial data input and output input data from the si pin is captured when this signal rises and serial data from the so pin is output when it falls. iC 7 so outputs serial data and status signal o undefined 8 si serial data input pin i C 9 xtalen crystal oscillation control pin. be sure to input the reset signal before stopping crystal oscillation. when the status shifts from crystal oscillation stop mode to normal mode, input the reset signal after crystal oscillation has stabilized. xtalen = l: normal mode xtalen = h: crystal oscillation stop mode iC 10 d.v dd positive power supply pin to logic circuit C C 11 da.v dd positive power supply pin to d/a converter block C C 12 rout r-ch audio signal output pin ao undefined 13 da.gnd d/a converter block gnd C C 14 regc scf regulator external capacitor connection pin aC C 15 da.gnd d/a converter block gnd C C 16 lout l-ch audio signal output pin ao undefined 17 da.v dd positive power supply pin to d/a converter block C C 18 r+ l 19 rC right channel sound data output pin. pwm output o h 20 lC h 21 l+ left channel sound data output pin. pwm output o l 22 x.v dd positive power supply pin to crystal oscillator C C 23 xtal crystal oscillator connection pin (input) i C 24 xtal crystal oscillator connection pin (output) o C 25 x.gnd crystal oscillator gnd C C 26 d.v dd positive power supply pin to logic circuit C C 27 emph subcode q pre-emphasis information output pin when applying emphasis, a high level is output. commands can be used to switch polarity. f6h lsb ep = 0: normal output ep = 1: inverted output o undefined
preliminary product information s14470ej1v1pm00 8 m m m m pd63711 pin no. pin name description i/o initial value 28 flag flag output pin indicating that the data currently being output was configured with uncorrectable data. (active high) o undefined 29 din serial data input pin to on-chip dac if a dsp (etc.) is not connected, this must be shorted with the dout pin. iC 30 dout serial sound data output pin o l 31 sckin serial clock input pin to on-chip dac i C 32 scko sound data output from dout changes with the falling of this clock. ensure that the system c onnected in the next stage captures the data at the rising of this signal. o undefined 33 lrckin lrck signal input pin to on-chip dac i C 34 lrck signal that distinguishes left channel and right channel of sound data output from dout o undefined 35 hold/ wdck defect detection output pin (hold) pin that outputs a signal twice the frequency of lrck (88.2 khz) (wdck) hold and wdck can be switched by microcontroller. o undefined 36 tx data output pin of digital audio interface o l 37 d.gnd logic circuit gnd C C 38 c16m buffering output pin of oscillation clock o C 39 limit the state of this pin is output in bit5 of the status output. i C 40 d.v dd positive power supply pin to logic circuit C C 41 lock efm synchronization detection signal this is high level if the frame counter output matches the synchronization pattern detection signal in the efm demodulation block, and low level if they do not match. o undefined 42 rfck frame synchronization signal of xtal system this is the divided crystal resonator clock and indicates a period of one frame (7.35 khz). o undefined 43 mirr/ wfck mirror output pin (mirr) frame synchronization signal of pll system. this si gnal is a signal with a frequency that is a division of the basic frequency (44.1 khz) of the read signal acquired from the pll system and is approximately equal to 1 frame cycle (7.35 khz) (wfck). mirr and wfck can be switched by microcontroller. o undefined 44 plck pin for bit clock monitor when a pll lock occurs, the falling edge of this signal lo cks to the efm si gnal. o undefined 45 d.gnd logic circuit gnd C C 46 c1d1 47 c1d2 output pins that indicate the results of c1 error correction these pins are defined until the falling edge of rfck. o undefined 48 c2d1 49 c2d2 50 c2d3 output pins that indicate the results of c2 error correction these pins are defined until the falling edge of rfck. o undefined 51 d.v dd positive power supply pin to logic circuit C C 52 pack pack synchronization signal of cd-text the fall of this signal indicates the beginning of the pack. o undefined
preliminary product information s14470ej1v1pm00 9 m m m m pd63711 pin no. pin name description i/o initial value 53 tso cd-text data serial output pin o undefined 54 tsi cd-text control parameter serial input pin i C 55 tsck cd-text serial clock input pin i C 56 tstb cd-text parameter strobe signal input pin i C 57 d.gnd logic circuit gnd C C 58 test0 59 test1 test pins. normally, connect to gnd. i C 60 atest test pin. normally, leave open. ao undefined 61 a.gnd analog circuit gnd C C 62 fd focus drive output pin ao ? a.v dd 63 td tracking drive output pin ao ? a.v dd 64 sd sled drive output pin ao ? a.v dd 65 md spindle drive output pin ao ? a.v dd 66 dac0 dac output pin for adjustment. outputs cram 7fh setting value. ao ? a.v dd 67 dac1 dac output pin for adjustment. outputs cram 7ch setting value. (on-chip rf fe amplifier offset) ao ? a.v dd 68 dac2 dac output pin for adjustment. outputs cram 7dh setting value. ao ? a.v dd 69 dac3 dac output pin for adjustment. outputs cram 7eh setting value. (on-chip rf te amplifier offset) ao ? a.v dd 70 a.v dd positive power supply pin to analog circuit C C 71 efm efm signal output pin o undefined 72 asy efm comparator reference voltage input pin ai C 73 c3t capacitor connection pin for 3t detection aC C 74 rfi rf signal input pin for efm data generation ai C 75 agco rf signal output pin after gain adjustment ao ? a.v dd 76 agci rf-agc amplifier input pin ai ? a.v dd 77 rfo rf summing amplifier output pin ao undefined 78 eq2 79 eq1 rf amplifier equalizer parts connection pin aC C 80 rf- rf summing amplifier inverse input pin ai C 81 a.gnd analog circuit gnd C C 82 a photo-detector a input pin ai ? a.v dd 83 c photo-detector c input pin ai ? a.v dd 84 b photo-detector b input pin ai ? a.v dd 85 d photo-detector d input pin ai ? a.v dd 86 f photo-detector f input pin ai ? a.v dd 87 e photo-detector e input pin ai ? a.v dd 88 a.v dd positive power supply pin to analog circuit C C 89 refout reference potential output pin ao ? a.v dd 90 fe- focus error amplifier inverse input pin ai ? a.v dd
preliminary product information s14470ej1v1pm00 10 m m m m pd63711 pin no. pin name description i/o initial value 91 feo focus error amplifier output pin ao ? a.v dd 92 te- tracking error amplifier inverse input pin ai ? a.v dd 93 teo tracking error amplifier output pin ao ? a.v dd 94 te2 pin from which tracking error is output after amplification ao ? a.v dd 95 tec tracking comparator input pin inputs a tracking error signal whose dc component is cut. a tracking zero-cross is detected inside the lsi using this signal. ai C 96 a.gnd analog circuit gnd C C 97 pd pd detection signal input pin for ld output monitor ai gnd 98 ld ld control current output pin ao undefined 99 pn apc circuit control polarity setting pin i C 100 a.v dd positive power supply pin to analog circuit C C cautions 1. do not allow any input pin to exceed the power supply voltage. 2. make each power supply voltage (d.v dd , a.v dd , x.v dd , da.v dd ) the same potential. remark the meanings of symbols in the i/o column are as follows. i: logic level input pin o: logic level output pin ai: analog input pin ao: analog output pin a - : analog parts connection pin reset input in the m pd63711, when the reset signal (active low) is input from the rst pin (pin 3) while the clock is being input from the xtal pin (pin 23), it takes up to 20 clocks (about 1.2 m s) before the statuses of all the pins are defined. to allow for this, therefore, be sure to input the reset signal for a sufficient amount of time. v dd xtal rst 20 t cy or more
preliminary product information s14470ej1v1pm00 11 m m m m pd63711 cautions on using the xtalen pin when stopping oscillation using the xtalen pin, note the following. 1. when stopping oscillation immediately after the power supply is turned on. the clock must be supplied while the reset signal is active, as in the above chart, even when stopping oscillation immediately after turning on the power supply. 2. when stopping oscillation in the normal use state (5 v) v dd xtalen rst be sure to set the reset signal to active before stopping oscillation. if oscillation is stopped without setting the reset signal to active, output of the servo drive or sound will stop or become unstable, which may cause bugs in external devices. time until resonator oscillation stabilizes. v dd xtalen rst "l"
preliminary product information s14470ej1v1pm00 12 m m m m pd63711 2. digital filter flowcharts flowcharts of the digital filters are shown below. fs = 176.4 khz. (1) focus filter 02h disturbance 01h fe 0ah + 00h g1 z ? 03h z ? 0bh ++ 0ch z ? 0fh + 0dh + z ? 0eh z ? 10h + z ? 11h 2 08h + z ? 04h + 05h z ? 06h + z ? 07h + 09h 2 + 16 fd z ? 59h + 58h g2 + 56h + 57h absolute value fzd fzc fs 16 1 fs 64 1 fs 4 1 + 48h z ? 49h + 4ah z ? 4bh + 4ch + 4dh focus search fs 1024 1 fs 64 1
preliminary product information s14470ej1v1pm00 13 m m m m pd63711 (2) tracking and sled filters remark bank 1 addresses are shown in parentheses. 14h disturbance 13h te 1ch + 12h g1 z e1 15h z e1 1dh ++ 1fh z e1 22h + 20h + z e1 21h z e1 23h + z e1 24h 2 1ah + z e1 16h + 17h z e1 18h + z e1 19h + 1bh 2 + 16 td g2 fs 16 1 (25h) (26h) (27h) (2fh) (30h) (32h) (35h) (33h) (34h) (36h) (37h) (2dh) (28h) (29h) (2ah) (2bh) (2ch) (2eh) + 1eh jump 61h z e1 62h + (31h) z e1 47h + 46h z e1 39h + 38h 3bh + 3ah z e1 3dh 43h + 42h z e1 thold z e1 40h + z e1 41h + 3ch + 3eh 3fh sd kick 45h + 44h z e1 fs 64 1 off on defect fs 128 1 fs 2048 1 defect defect +
preliminary product information s14470ej1v1pm00 14 m m m m pd63711 (3) spindle system mdp 51h 4eh 4fh + 2 55h + md 54h z ? 52h + z ? 53h mds z ? 50h + note fs 4 1 note this switch is controlled according to the clv lock decision signal (same signal as fr bit in status signal). asynchronous state: fr = 0 ? switch is down synchronous state: fr = 1 ? switch is up (4) mirr signal 5ah mirenv z ? 5ch + 5bh 5eh + mirr 5fh peak g1o 60h 5dh offset + 0.5 0.5 (5) rfok signal 64h rfenvh + rfok 65h fs 8 1 (6) gain detection filter g1 66h z ? 69h + 67h + z ? 68h z ? 6ah + z ? 6bh 2 6dh fs 4 1 absolute value g1o z ? 6ch + g2 66h z ? 69h + 67h + z ? 68h z ? 6ah + z ? 6bh 2 6dh fs 4 1 absolute value g2o z ? 6ch + + +
preliminary product information s14470ej1v1pm00 15 m m m m pd63711 (7) balance adjustment filter 66h z ? 67h + 6ch g1o z ? 6bh + te fe 68h peak 69h + 6fh 6eh g2o z ? 6dh + bottom 6ah 70h - fs 4 1 (8) 3t detection filter 71h 3tenv z e1 72h + g1o detection 74h z e1 75h + 76h fe + 73h fs 4 1
preliminary product information s14470ej1v1pm00 16 m m m m pd63711 3. microcontroller interface commands 3.1 servo system commands table 3-1. servo system command functions command function reference 00h writing data to cram C 01h cram address setting C 10h servo control 0 p.18 11h servo control 1 p.20 12h servo control 2 p.22 13h focus search setting p.23 14h disturbance generation and so data output settings p.24 15h half-wave brake control p.26 17h disturbance frequency and level settings p.27 18h defect comparator level setting p.28 22h 23h 24h track jump kick time setting, traverse counter setting p.29 table 3-2. list of servo system commands (1/2) parameter (data) command (command code) msb654321lsb 00h writing data to cram 01h cram address 10h sk tm teh fr tk tb tcnt brk 11h fon ton son mon fst dfct jsk tab 12h balon sdmsk sdl1 sdl0 dfctt scv 0 tfp 13h 000000t1t0 14h gst gon gft t/3 g/b sel2 sel1 sel0 15h balsw 0 0 0 bklmt 0 0 0 17h fd2 fd1 fd0 frq4 frq3 frq2 frq1 frq0 18h df7 df6 df5 df4 df3 df2 df1 df0 22h 0 track kick time a 23h 0 track kick time b/traverse counter n (h) 24h traverse counter n (l)/track jump counter
preliminary product information s14470ej1v1pm00 17 m m m m pd63711 table 3-2. list of servo system commands (2/2) cram address cram data 77h track kick level a (kick level) 78h track kick level b (brake level) 79h sled kick level 7ah sled dead zone level setting (C) 7bh sled dead zone level setting (+) 7ch dac level setting for adjustment (dac1 pin output) (on-chip rf fe amplifier offset) 7dh dac level setting for adjustment (dac2 pin output) 7eh dac level setting for adjustment (dac3 pin output) (on-chip rf te amplifier offset) 7fh dac level setting for adjustment (dac0 output) caution do not send an undefined command.
preliminary product information s14470ej1v1pm00 18 m m m m pd63711 (1) 10h command (servo control 0) 00010000 msb command lsb sk tm teh fr tk tb tcnt brk msb parameter lsb brk half-wave brake circuit 0 - - - 1on tcnt function of tk bit 0 start of track jump sequencer 1 load value in traverse counter tb tracking filter coefficient bank 0 bank 0 1 bank 1 tk track jump/load trigger 0 1 execute operation specified by tcnt bit fr output polarity switching 0 output level - 1 1 leave output level unchanged teh error hold function on track jump 0 hold reference (data 00) 1 hold previous value tm tracking mute 0 output results of tracking filter (normal operation) 1 output value specified by teh bit sk sled kick 0 1 execute sled kick
preliminary product information s14470ej1v1pm00 19 m m m m pd63711 [functional description] brk: controls the half-wave brake circuit. 1 half-wave brake circuit is on tcnt: used in combination with the tk bit. 0 if tk = 1 is set, start a track jump sequencer 1 if tk = 1 is set, load the values of registers 23h and 24h in the traverse counter tb: switches the tracking filter coefficient bank. 0 tracking filter bank 0 1 tracking filter bank 1 tk: this is the track jump trigger and traverse counter load control. it has two meanings depending on the t.cnt bit. an operation using the tk bit is a one-shot operation that operates only in the instant this is set to 1. fr: controls the output level polarity when tracking and sled kicking. 0 output the value in the output level register (cram 77h to 79h) multiplied by - 1 1 output the value in the output level register unchanged teh: controls the error hold function when track jumping. selects tracking output when sk = tm = 1. 0 hold reference 1 hold previous value tm: controls tracking mute. 0 output the arithmetic result of the tracking filter (normal operation) 1 either hold the previous value or hold a reference (data value 00) depending on the teh bit specification sk: controls sled kick. 1 perform sled kick using the value set in cram 79h
preliminary product information s14470ej1v1pm00 20 m m m m pd63711 (2) 11h command (servo control 1) 00010001 msb command lsb fon ton son mon fst dfct jsk tab msb parameter lsb tab track jump sequencer 0 - - - - 1 halt operation jsk sled kick 0 1 execute sled kick dfct error hold output upon defect detection 0no 1 yes fst focus search 0 1 start focus search mon spindle servo output 0 off (d/a output stopped, 1/2 a.v dd ) 1on son sled servo output 0 off (d/a output stopped, 1/2 a.v dd ) 1on ton tracking servo output 0 off (d/a output stopped, 1/2 a.v dd ) 1on fon focus servo output 0 off (d/a output stopped, 1/2 a.v dd ) 1on
preliminary product information s14470ej1v1pm00 21 m m m m pd63711 [functional description] tab: controls close of track jump sequencer operation. 1 halt track jump sequencer operation an operation using the tab bit is a one-shot operation that operates only on the instant this is set to 1. jsk: controls sled kick when track jumping. 1 perform sled kick in the track jump period using the level set in cram 79h dfct: controls error hold output on defect detection. 0 no hold output all switches controlled by a defect signal in the focus filter and tracking filter are fixed in the up position (normal position). 1 hold output switch the above switches according to the defect signal state. fst: focus search control. 1 start focus search fon must be 1 at this time. mon: controls whether spindle servo output (d/a output) is on or off. 0 d/a output is off, output 1 2 a.v dd 1 d/a output is on son: controls whether sled servo output (d/a output) is on or off. 0 d/a output is off, output 1 2 a.v dd 1 d/a output is on ton: controls whether tracking servo output (d/a output) is on or off. 0 d/a output is off, output 1 2 a.v dd 1 d/a output is on fon: controls whether focus servo output (d/a output) is on or off. 0 d/a output is off, output 1 2 a.v dd 1 d/a output is on
preliminary product information s14470ej1v1pm00 22 m m m m pd63711 (3) 12h command (servo control 2) 00010010 msb command lsb balon sdmsk sdl1 sdl0 dfctt scv 0 tfp msb parameter lsb tfp output polarity of tec pin 0 normal 1 inverted scv sled servo control by clv lock 0 sled servo off when clv is unlocked 1 sled servo always on dfctt input hold time limit 0 approximately 2.8 ms 1 approximately 1.4 ms sdmsk 1 2.9 ms balon dac pin output 0 1/2 a.v dd 1 dc voltage based on setting 1 1 11.6 ms 1 0 (none) 0 sdl1 sdl0 sled kick time after track jump 00 01 10 11 1.4 ms 5.8 ms (resolution = 180 s) m [functional description] tfp: tec signal (tracking error zero-cross signal) polarity control. 0 normal output 1 inverted output scv: sled servo control by clv lock. 0 sled servo is off (d/a output halted) when clv is unlocked (when fr bit in status signal is 0) 1 sled servo is always on regardless of clv lock at the time of a sled kick, d/a output is performed regardless of a clv lock. dfctt: sets the tracking or focus input hold time limit when the absence of an rf signal is detected. 0 approximately 2.8 ms 1 approximately 1.4 ms sdmsk, sdl[1:0]: sets the sled kick time after a track jump. balon: sets dac0 to dac3 pin outputs. this bit is set to 0 on a reset. 0 output 1 2 a.v dd 1 output dc voltage set using cram 7fh, 7ch, 7dh, and 7eh from dac0 to dac3 pins respectively
preliminary product information s14470ej1v1pm00 23 m m m m pd63711 (4) 13h command (focus search setting) 00010011 msb command lsb 000000t1t0 msb parameter lsb t1 square wave period on focus search 0 approximately 0.37 s 0 approximately 0.74 s t0 0 1 1 approximately 1.49 s 0 1 approximately 2.97 s 1 [functional description] t[1:0]: sets the period of the square wave for focus search. period as shown below, square wave output on focus search is begun from the time one quarter of the period has gone by. period 1 period focus search square wave focus search start command 4 1
preliminary product information s14470ej1v1pm00 24 m m m m pd63711 (5) 14h command (disturbance generation and so data output setting) [functional description] sel[2:0]: sets so data output. g/b, t/3: sets data to latch to g1 and g2 registers inside the lsi. gft: selects the disturbance feed destination. gon: controls whether disturbance feed to the te or fe filters is on or off. gst: controls fetching of arithmetic result of filter for gain detection. 1 arithmetic result of filter for gain detection (g1o, g2o) is latched to g1 and g2 registers inside lsi (during which time so pin outputs high level and is in busy state) 00010100 msb command lsb gst gon gft t/3 g/b sel2 sel1 sel0 msb parameter lsb gft disturbance feed destination selection (selects signal input to balance detection filter) 0 focus equalizer (fe signal) 1 tracking equalizer (te signal) gon feed of disturbance to te or fe filter on/off 0 disturbance off 1 disturbance on gst fetch arithmetic result of filter for gain detection 0 - 1 fetch sel2 0 te 0 1 g2 1 sel1 sel0 so data output 10 11 00 01 fe g1 t/3 output data to g1 and g2 0 gain detection results 0 data of filter for tracking balance adjustment (te peak, te bottom) g/b 0 1 1 rf amplitude detection results 0 1 3t detection results 1
preliminary product information s14470ej1v1pm00 25 m m m m pd63711 on data readout from the serial interface using the 14h command, the following one-bit shift processing toward the msb is executed for g1 and g2 data read from the serial interface by means of the settings of t/3 and g/b bits. figure 3-1. data readout block 1514131211109876543210 msb lsb 76543210 from signal flow double the aim of one-bit shift processing toward the msb is to improve the bit precision of values that are read. for filters such as the gain detection filter, which always output positive values, the sign bit has no meaning. by performing one-bit shift processing toward the msb on values read from the serial interface in the m pd63711, the precision of a value that is read is improved by one bit from reading the lsb bit instead of the sign bit. when reading sign output (positive and negative values) as in the case of balance detection, as a procedure for avoiding losing a sign due to one-bit shift processing toward the msb, multiply (shift one bit to the right) a value less than 0.5 in the final output stage multiplier in advance. by doing so, the correct sign value is read.
preliminary product information s14470ej1v1pm00 26 m m m m pd63711 (6) 15h command (half-wave brake control) 00010101 msb command lsb balsw 0 0 0 bklmt 0 0 0 msb parameter lsb bklmt half-wave brake control 0 - 1 half-wave brake off at or above approximately 1.4 ms balsw tbal or fbal detection filter internal sw 0 off 1on [functional description] bklmt: controls half-wave brake circuit 1 half-wave brake is off at or above approximately 1.4 ms balsw: controls addition/subtraction switch inside tracking or focus balance detection filter. 0 off 1 on
preliminary product information s14470ej1v1pm00 27 m m m m pd63711 (7) 17h command (disturbance frequency and level setting) 00010111 msb command lsb fd2 fd1 fd0 frq4 frq3 frq2 frq1 frq0 msb parameter lsb frq[4:0] disturbance frequency setting fd[2:0] disturbance level setting [functional description] frq[4:0]: sets the disturbance frequency (5-bit absolute value). fd[2:0]: sets the disturbance level (3-bit absolute value). the disturbance frequency and disturbance level are calculated using the following expressions. frequency (f) = fs (fq + 1) 4 level (h) = fd (fq + 1) fs: 176.4 khz = 88.2 khz 2 fq: value set in frq[4:0] fd: value set in fd[2:0] caution set fd to the greatest value that satisfies h 127. 0 h h f example when 17h register = b5h b5h = 10110101b ? fd = 101b, fq = 10101b since fq = 21, 88.2 khz = 1.0 khz f = (21 + 1) 4 since fd = 5, h = 5 (21 + 1) = 110 = 6eh 17h register = d5h is not possible because fd = 6, h = 6 (21+1) = 132, and h then exceeds 127.
preliminary product information s14470ej1v1pm00 28 m m m m pd63711 (8) 18h command (defect comparator level setting) 00011000 msb command lsb df7 df6 df5 df4 df3 df2 df1 df0 msb parameter lsb df[7:0] defect comparator level [functional description] df[7:0] : set the defect signal comparator level. the range of 1 a.v dd a.v dd 2 1 4 can be set in 256 8-bit levels. the setting value becomes the comparison threshold value. the comparison result has the inverse polarity of the input (because the msb after subtracting is used). output is inverted (because the signal after comparator output handled as a signal absence detection by defect = h). the relationship between comparator level setting values and defect envelope signal voltages is shown below. df[7:0] defect envelope defectenv defect msb df[7:0] output with inverse polarity polarity inversion polarity inversion comparator 3 4 a.v dd 1 4 a.v dd 7fh (2's) 80h (2's)
preliminary product information s14470ej1v1pm00 29 m m m m pd63711 (9) 22h, 23h, and 24h commands (track jump control) [functional description] track jump 22h: the kick time setting 7 bits wide. always set the msb to 0. the kick time is calculated using the following expression. (setting value + 1) 1 176.4 khz kick time = (fs = = 88.2 khz) fs 2 23h: brake time setting 7 bits wide. always set the msb to 0. the brake time is calculated using the following expression. (setting value + 1) 1 176.4 khz brake time = (fs = = 88.2 khz) fs 2 24h: track counter setting 7 bits wide. always set the msb to 0. the value set in 24h is used as a counter value. traverse count 23h: traverse counter setting (higher 7 bits, always set msb to 0) 24h: traverse counter setting (lower 8 bits) the values set in 23h and 24h (15 bits wide) are used as counter values. 23h and 24h are used both when track jumping and when counting traverses, and are switched according to the setting of the tcnt bit of the 10h command. 00100010 msb command lsb 0 d6d5d4d3d2d1d0 msb parameter lsb d[6:0] track kick time a 00100100 msb command lsb d7 d6 d5 d4 d3 d2 d1 d0 msb parameter lsb d[7:0] traverse counter n (l)/ track jump counter 00100011 msb command lsb 0 d6d5d4d3d2d1d0 msb parameter lsb d[6:0] track kick time b/traverse counter n (h)
preliminary product information s14470ej1v1pm00 30 m m m m pd63711 3.2 rf system commands table 3-3. functions of rf system commands command function reference 30h agc amplifier gain setting, rf amplifier offset setting p.31 31h 3t component detection gain setting, 3t detection circuit lpf setting, te amplifier gain setting p.32 32h fe, rf, and te amplifier gain settings p.33 33h te amplifier balance setting p.34 34h mirr detection block peak and bottom time constant settings, te2 signal gain setting p.35 35h 3t component extraction from rf signal timing setting p.37 36h efm output block buffer setting, rf amplifier external load resistor setting p.38 37h setting of output to atest pin, fe and te amplifier load resistors setting p.39 39h playback speed setting, eq speed selection ( 1 or 2), apc amplifier polarity selection, current input type setting p.40 table 3-4. list of rf system commands parameter (data) command (command code) msb654321lsb 30h drf3 drf2 drf1 drf0 ga3 ga2 ga1 ga0 31h gtu1 gtu0 f31 f30 gf5 g32 g31 g30 32h gt2 gt1 gt0 gf4 gf3 gf2 gf1 gf0 33h tb6 tb5 tb4 tb3 tb2 tb1 tb0 ivs2 34h tm3 tm2 tm1 gtec sost tm5 tm4 tmc 35h 0 3ts6 3ts5 3ts4 3ts3 3ts2 3ts1 3ts0 36h deqo gr2 gr1 gr0 seq 0 0 efmo 37h tfo tto 0 0 0 ts3 tsd tsm 39h lds 0 ivs sw2 apn 0 0 cv2 caution do not send an undefined command.
preliminary product information s14470ej1v1pm00 31 m m m m pd63711 (1) 30h command (settings of agc amplifier gain and rf amplifier offset) remark the mark * indicates the contents set after a reset. [functional description] ga[3:0]: used in setting the agc amplifier gain. perform gain setting while monitoring the mirr signals (peak) - (bottom) signal. the 37h command can be used to output the value of a mirr signal from the atest pin before a/d conversion. in addition, in order to monitor amplitude stably, make adjustments by using the 34h command to maximize the time constant. drf[3:0]: used in setting the rf amplifier output dc voltage. can be cancelled using deqo in the 36h command. 00110000 msb command lsb drf3 drf2 drf1 drf0 ga3 ga2 ga1 ga0 msb parameter lsb ga3 1 - 4.0 db 1 1 ga2 ga1 agc amplifier gain 00 00 01 - 5.0 db - 3.0 db ga0 0 1 0 1 - 1.5 db 1 1 01 10 10 - 2.1 db - 1.0 db 1 0 1 1 11 - 0.4 db 0 1 * +1.0 db 0 0 11 00 00 +0.2 db +1.7 db 1 0 1 0 +3.1 db 0 0 01 01 10 +2.4 db +4.2 db 0 1 0 0 +6.4 db 0 0 10 11 11 +5.3 db +7.5 db 1 0 1 drf3 1 2.00 v 1 0 drf2 drf1 rf amplifier output dc voltage note 10 00 10 2.25 v 1.75 v drf0 0 0 0 0 1.00 v 0 0 01 00 01 1.25 v 0.75 v 0 1 1 0 00 * 1.50 v 0 note values shown here are standard values, not rated values.
preliminary product information s14470ej1v1pm00 32 m m m m pd63711 (2) 31h command (settings of 3t component detection gain, 3t detection circuit lpf, and te amplifier gain) remark the mark * indicates the contents set after a reset. [functional description] g3[2:0]: used in setting the 3t detection circuit sensitivity. when disturbance is injected into the fe system, an amplitude of approximately 2.0 v p-p is obtained in the default state when the rf signal fluctuates 20%. f3[1:0]: the lpf for eliminating noise after s/h in the 3t detection circuit. since s/h samples using an efm high frequency signal, lpf is set for stability. gf5: adjusts the fe amplifier gain. changes the input resistor value of the fe amplifier second stage. used with the gf4 bit of the 32h command. gtu[1:0]: used to raise the te amplifier gain. switches the gain by changing the input resistor value. note that gtu0 and gtu1 cannot be used together. 00110001 msb command lsb gtu1 gtu0 f31 f30 gf5 g32 g31 g30 msb parameter lsb g32 1 +14.0 db 1 1 * +20.0 db 0 g31 g30 3t detection circuit gain 01 10 11 00 +8.0 db +16.5 db +23.5 db 0 01 +26.0 db 0 10 +28.0 db 0 11 f31 3t circuit lpf after s/h 1 fc = 50 khz 0 * fc = 100 khz f30 0 0 0 fc = 200 khz 1 gf5 fe amplifier gain adjustment 1 +2.5 db 1 - 2.0 db gf4 1 0 0 +6.0 db 1 0 * 0 db 0 gtu1 te amplifier gain adjustment 0 * +14 db (on gain typ setting of 32h command) 0 +6 db up gtu0 0 1 1 +12 db up 0
preliminary product information s14470ej1v1pm00 33 m m m m pd63711 (3) 32h command (fe, rf, and te amplifier gain settings) remark the mark * indicates the contents set after a reset. [functional description] gf[2:0]: sets the fe amplifier and rf amplifier gain. raising/decreasing the gain can be performed in 6-db units and can be set in variations of five stages. gf3: raises the fe amplifier and rf amplifier gain +6 db. changes the resistor value of first-stage amplifier input. gf4: adjusts the fe amplifier gain. used with the gf5 bit of the 31h command. gt[2:0]: sets the te amplifier gain. raising/decreasing the gain can be performed in 6-db units and can be set in variations of seven stages. 00110010 msb command lsb gt2 gt1 gt0 gf4 gf3 gf2 gf1 gf0 msb parameter lsb gf2 0 +19.0 db/+25.0 db 1 0 +13.0 db/+19.0 db 1 gf1 gf0 fe/rf amplifier gain 10 10 00 01 +22.0 db/+28.0 db * +16.0 db/+22.0 db +10.0 db/+16.0 db 0 01 gf3 fe/rf amplifier gain adjustment 1 +6 db up 0 * +16 db/+22 db (on gain typ setting with gf[2:0]) gf4 fe amplifier gain adjustment refer to gf5 bit of 31h command gt2 1 +10.5 db 1 1 * +14.0 db 0 gt1 gt0 te amplifier gain 01 10 11 00 +8.0 db +12.5 db +15.5 db 0 01 +17.5 db 0 10 +20.0 db 0 11
preliminary product information s14470ej1v1pm00 34 m m m m pd63711 (4) 33h command (te amplifier balance setting) remark the mark * indicates the contents set after a reset. [functional description] ivs2: sets e and f pins to the current input mode. when using this mode, be sure to set the ivs bit of the 39h command to 1. tb[6:0]: prior stage to the te amplifier. sets the photo-detector e and f signal gains. switching is possible in 128 ways over an adjustment range of 5 db. 00110011 msb command lsb tb6 tb5 tb4 tb3 tb2 tb1 tb0 ivs2 msb parameter lsb tb[6:0] e/f gain note 1000000 11.42 db/16.50 db 1000001 11.48 db/16.47 db 1000010 11.53 db/16.44 db ~ 1111111 13.96 db/14.04 db 0000000 * 14.00 db/14.00 db 0000001 14.04 db/13.96 db ~ 0111101 16.44 db/11.53 db 0111110 16.47 db/11.48 db 0111111 16.50 db/11.42 db (128 divisions) note values shown above are standard values, not rated values. note selected with ivs bit of 39h command. ivs2 te amplifier current input mode 1 only e and f pins are in the current input mode 0 * all a to f pins are in the current input mode note
preliminary product information s14470ej1v1pm00 35 m m m m pd63711 (5) 34h command (settings of mirr detection block peak and bottom time constants and te2 signal gain) 00110100 msb command lsb tm3 tm2 tm1 gtec sost tm5 tm4 tmc msb parameter lsb tmc mirr/defect time constants 1 set to pc2572 ratio 0 * follow tm[3:1] settings m sost fe output offset control sw 1 offset injection using cram 7ch 0 * no offset injection gtec te2 signal gain 1 +24.0 db (te 3) 0 * +26.0 db (te 4) tm3 1 1 1 0 tm2 tm1 mirr peak/bottom/defect bottom time constants 01 10 11 00 8 s/v/40 s/v/40 s/v mmm 0 01 0 10 0 11 10 s/v/50 s/v/50 s/v mmm 14 s/v/70 s/v/70 s/v mmm * 20 s/v/100 s/v/100 s/v mmm 27 s/v/140 s/v/140 s/v mmm 40 s/v/200 s/v/200 s/v mmm 50 s/v/250 s/v/250 s/v mm m tm5 1 0 0 tm4 defect time constant ratio 0 1 0 change the defect time constant to 1/4 change the defect time constant to 1/2 * follow tm[3:1] and tmc settings remark the mark * indicates the contents set after a reset.
preliminary product information s14470ej1v1pm00 36 m m m m pd63711 [functional description] tmc: changes mirr/defect time constants to the m pc2572 ratio. example mirr peak/bottom/defect bottom = 20 m s/v/400 m s/v/100 m s/v (when tm[5:4] = [0:0], tmc = 1, tm[3:1] time constants is typ) tm[5:4]: of the mirr/defect time constants set using tm[3:1], changes only the defect detection time constant. valid only when tmc is set to 1. example mirr peak/bottom/defect bottom = 20 m s/v/400 m s/v/50 m s/v (when tm[5:4] = [0,1], tmc = 1, and tm[3:1] time constant is typ) sost: controls the offset level of the on-chip fe amplifier using cram 7ch. gtec: used in setting the te2 signal gain. this setting can be used to set the te2 signal gain to 3 times or 4 times that of the te signal. tm[3:1]: used in setting the mirr/defect circuit peak and bottom time constants. mirr signal generation.............a mirr signal is generated by superimposing rf (peak) - (bottom) detection waveform on dc 1.5 v and comparing them to a fixed value after a/d conversion. set an arbitrary comparator level in cram 5fh. defect signal generation .......a defect signal is generated by superimposing rf bottom detection signals centered around dc 2.5 v and comparing them to a fixed value after a/d conversion. set an arbitrary comparator level using the 18h command. agc amplifier adjustment .........agc amplifier control can be adjusted using the mirr signal generation filter after a/d conversion. to monitor rf amplitude (g1o) stably, adjust with the mirr time constant (cram 5dh) in its the longest state. the mirr and defect signals before a/d conversion can be monitored at the atest pin using the 37h command.
preliminary product information s14470ej1v1pm00 37 m m m m pd63711 (6) 35h command (setting of timing for 3t component extraction from rf signal) 00110101 msb command lsb 0 3ts6 3ts5 3ts4 3ts3 3ts2 3ts1 3ts0 msb parameter lsb 3ts2 0 14.9 ns (7.46 2) 0 0 29.8 ns (7.46 4) 0 3ts1 3ts0 3t extraction pulse width 00 01 10 11 * 7.46 ns 22.4 ns (7.46 3) 37.3 ns (7.46 5) 1 00 44.8 ns (7.46 6) 1 01 52.2 ns (7.46 7) 1 10 59.7 ns (7.46 8) 1 11 3ts6 0 59.6 ns (29.8 2) 0 0 119.2 ns (29.8 4) 0 3ts5 3ts4 3t extraction pulse delay 00 00 01 01 * 29.8 ns 89.4 ns (29.8 3) 149.0 ns (29.8 5) 0 10 178.8 ns (29.8 6) 0 10 208.6 ns (29.8 7) 0 11 238.4 ns (29.8 8) 0 11 3ts3 0 1 0 1 0 1 0 1 59.6 ns 1 1 178.8 ns (59.6 3) 1 00 00 01 119.2 ns (59.6 2) 238.4 ns (59.6 4) 1 01 298.0 ns (59.6 5) 1 10 357.6 ns (59.6 6) 1 10 417.2 ns (59.6 7) 1 11 0 1 0 1 0 1 0 476.8 ns (59.6 8) 1 111 remark the mark * indicates the contents set after a reset. [functional description] 3ts[6:0]: sets the timing for extracting 3t components from rf signals. note that if this value is not set accurately, 11t and not 3t detection sensitivity will be high.
preliminary product information s14470ej1v1pm00 38 m m m m pd63711 (7) 36h command (settings of efm output block buffer and rf amplifier external load resistor) remark the mark * indicates the contents set after a reset. [functional description] efmo: sets efm comparator output buffer on or off. normally, chattering is avoided by using a 2-k w resistor on output. seq: used when there is an externally attached rf amplifier load. gr[2:0]: used in fine tuning of rf gain when an rf amplifier load is externally attached. performed by dividing the variation of 4 db into five stages. deqo: switches the rf amplifier output voltage. when an rfeq load resistor is externally attached, by setting this register to 2.5 v, the offset can be adjusted using the external resistor. 00110110 msb command lsb deqo gr2 gr1 gr0 seq 0 0 efmo msb parameter lsb efmo efm output buffer 1 output buffer on 0 * output buffer off seq rf output load 1 external rf load 0 * on-chip rf load gr2 1 +20.0 db 1 0 +24.0 db 0 gr1 gr0 rf gain fine adjustment 01 10 00 01 +18.0 db * +22.0 db (when fe/rf gain is typ) +26.0 db 0 10 deqo rfeq output dc offset switching 1 2.5 v (offset injection by external resistor) 0 * rfeq output 1.5 v
preliminary product information s14470ej1v1pm00 39 m m m m pd63711 (8) 37h command (settings of output to atest pin and fe and te amplifier load resistors) remark the mark * indicates the contents set after a reset. [functional description] tsm: when tsm = 1, the mirr signal is output from the atest pin. tsd: when tsd = 1, the defect signal is output from the atest pin. ts3: when ts3 = 1, the 3t signal is output from the atest pin. tto: selects whether the te amplifier load resistor is on-chip or external. the te amplifier on-chip load resistor is 80 k w when a current input type is selected, and 160 k w when a voltage input type is selected. tfo: selects whether the fe amplifier load resistor is on-chip or external. the fe amplifier on-chip load resistor is 80 k w . cautions 1. the atest pin is for monitoring. since its output drivability is not high, use it only for monitoring and normally leave it open. at the present stage, operation of the atest pin is not guaranteed. 2. do not set two or more of the bits tsm, tsd, and ts3 to 1 at one time. be sure to set only one of the bits to 1. 00110111 msb command lsb tfo tto 0 0 0 ts3 tsd tsm msb parameter lsb tsm output of mirr signal to atest pin 1 mirr signal monitor 0 * output off tsd output of defect signal to atest pin 1 defect signal monitor 0 * output off ts3 output of 3t signal to atest pin 1 3t signal monitor 0 * output off tto te amplifier load resistor 1 external load resistor 0 * on-chip load resistor used tfo fe amplifier load resistor 1 external load resistor 0 * on-chip load resistor used
preliminary product information s14470ej1v1pm00 40 m m m m pd63711 (9) 39h command (settings of playback speed, eq speed, apc amplifier polarity, and current input type) 00111001 msb command lsb lds 0 ivs sw2 apn 0 0 cv2 msb parameter lsb cv2 double-speed setting 1 set double-speed 0 * set single-speed apn apc circuit n-sub or p-sub selection 1 * apc circuit, n-sub supported 0 apc circuit, p-sub supported sw2 rfeq single or double sw selection 1 use circuit on pin 79 eq1 side 0 * use circuit on pin 78 eq2 side ivs selection of signal input method from pickup 1 current input type 0 * voltage input type lds apc circuit on or off selection 1 apc circuit operation (ld control current output) 0 * stop apc circuit operation (ld control current output stopped) remark the mark * indicates the contents set after a reset. [functional description] cv2: selects the playback speed (double-speed). apn: selects whether the apc circuit supports n-sub or p-sub. sw2: selects the rfeq circuit to use. ivs: set the appropriate value for the form of input from the pickup. lds: selects whether the apc circuit (ld drive current controller) is on or off.
preliminary product information s14470ej1v1pm00 41 m m m m pd63711 3.3 signal processing system commands table 3-5. functions of signal processing system commands command function reference f0h on or off selection for muting and attenuation, on or off selection for interpolate processing of uncorrectable data medium values, setting of number of interpolated frames for synchronization guard p.43 f1h clv servo control p.44 f2h readout-start q code address specification, peak level data readout p.45 f5h q code consecutive readout p.47 f6h lrck pin polarity switching emph pin polarity switching p.49 f7h attenuation on or off p.50 f8h nop (no target) p.50 fah attenuation amount setting (l-ch) p.51 fbh attenuation amount setting (r-ch) p.51 fch error correcting capability selection, on or off selection for subcode synchronization guard, forcible muting selection, bilingual mode selection, on or off selection for digital out p.52 fdh c bit setting p.53 feh digital attenuation amount setting p.53
preliminary product information s14470ej1v1pm00 42 m m m m pd63711 table 3-6. list of signal processing system commands parameter (data) command (command code) msb654321lsb f0h hlz0tma0 f1h d i 0 g t d2 d1 d0 f2h pr 0 0 0 a3 a2 a1 a0 f5h none f6h 0000 psel 0 lp ep f7h pwm 0 0 0 wd2 wd1 mon at2 f8h none fah l7l6l5l4l3l2l1l0 fbh r7r6r5r4r3r2r1r0 fch tx br bl t1 t0 s e1 e0 fdh s3s2s1s0 0 0 c1c0 feh 000000a1a0 caution do not send an undefined command.
preliminary product information s14470ej1v1pm00 43 m m m m pd63711 (1) f0h command (efm signal input and audio/cd-rom data output related parameter setting) 1111000 msb command hlz0tma msb lsb lsb parameter z 0 attenuation 1 on 0 0 setting prohibited 0 m a sound output 00 01 10 11 muting off * muting on 0 0 zero-cross muting off 1 00 setting prohibited 1 01 zero-cross muting on 1 10 setting prohibited 1 11 t interpolate processing of uncorrectable data medium values 0 * yes (cd mode) 1 no (cd-rom mode) h synchronization guard 0 2-frame interpolation 0 * 4-frame interpolation l 0 1 1 8-frame interpolation 0 1 16-frame interpolation 1 remark the mark * indicates the contents set after a reset. [functional description] z, m, a: selects on or off for muting and attenuation. t: selects cd mode or cd-rom mode. 0 cd mode when an uncorrectable error is detected in the upper or lower 8 bits of audio data (16 bits), it is output after performing interpolation. high level is output from the flag pin at the same time. 1 cd-rom mode even if an uncorrectable error is detected in the upper or lower 8 bits of cd-rom data (16 bits), it is output without performing interpolation. however, the flag pin outputs whether an error was detected in either the upper or the lower 8 bits. this makes highly accurate erasure correction possible in a cd-rom system connected to the m pd63711. h, l: interpolates the signal based on 588 counter when the frame synchronization signal is not in the window. this specifies the number of frames.
preliminary product information s14470ej1v1pm00 44 m m m m pd63711 (2) f1h command (clv servo control) 1111000 msb command di0gtd2d1 msb lsb lsb parameter d2 0 kick 0 0 setting prohibited 0 d1 d0 control state 00 01 10 11 * stop brake 1 d0 lead-in servo 1 00 rough servo 1 01 steady servo 1 10 adaptive servo 1 11 t peak hold period 0 * rfck/2 1 rfck/4 g lead-in servo gain 0 ?2 db 1 * 0 db i bottom hold period 0 * rfck/16 1 rfck/32 d steady servo phase comparison 0 * rfck/4 and wfck/4 1 rfck/8 and wfck/8 remark the mark * indicates the contents set after a reset. [functional description] d[2:0]: controls the clv servo. t: selects whether to make the peak hold period of the lead-in servo rfck/2 or rfck/4. g: selects whether to make the gain of the lead-in servo - 12 db or 0 db. i: selects whether to make the bottom hold period of the lead-in servo rfck/16 or rfck/32. d: selects whether to make the phase comparison signals of the steady servo rfck/4 and wfck/4 or rfck/8 and wfck/8.
preliminary product information s14470ej1v1pm00 45 m m m m pd63711 (3) f2h command (readout-start q code address specification and peak level data readout) 11110010 msb command lsb pr 0 0 0 a3a2a1a0 msb parameter lsb a3 0 tno 0 0 min 0 a2 a1 q code data 00 00 01 01 control, adr point or x sec 0 10 frame 0 10 zero 0 11 pmin or amin 0 11 a0 0 1 0 1 0 1 0 1 psec or asec 1 1 * ect 1 00 00 01 pframe or aframe pklu note 1 01 pkld note 1 10 pkru note 1 10 pkrd note 1 11 0 1 0 1 0 1 0 note the cc flag must be checked when reading peak level data. pr peak register clear 0* 1 peak register clear remark the mark * indicates the contents set after a reset. [functional description] this command reads out the q code data and peak level data indicated by parameters. q code data consists of 8-bit units, and arbitrary data (80 bits excluding the crc word) can be read by specifying a pointer address using parameters. the pointer addresses that can be specified using parameters are 00h through 0eh. do not specify addresses other than these. after data has been read out, the pointer address is incremented ( ? 0 ? 1 ? 2 ? ). q code data also can be read out using the f5h command. refer to the f5h command for details of the reading method. the q code data that can be read out using this command and the f5h command is frame data for which crc checking was ok. therefore, crc checking need not be performed on the microcontroller.
preliminary product information s14470ej1v1pm00 46 m m m m pd63711 the contents of the internal register ect of the lsi, which were read by ah parameter input following f2h command input, are described below. as shown below, the ect register consists of an error counter in the upper 4 bits and a frame counter in the lower 4 bits. e3 e2 e1 e0 f3 f2 f1 f0 msb lsb f[3:0] frame counter * f[3:0] = 0000 e[3:0] error counter * e[3:0] = 1111 remark the mark * indicates the contents set after a reset. [functional description] f[3:0]: whenever the q code is updated, the value of this counter is incremented (0 ? 1 ? ... ? f ? 0...). if a crc error occurs, the q code is not updated and the value of the counter does not change. e[3:0]: this counter indicates the crc error state. if a crc error occurs, the counter value is incremented (with a limit of fh). if an error does not occur, the value of the counter is reset (0h). peak level data is described below. pklu: l channel peak level data (upper 8 bits) pkld: l channel peak level data (lower 8 bits) pkru: r channel peak level data (upper 8 bits) pkrd: r channel peak level data (lower 8 bits) the maximum value of both the l channel and r channel in the a subcode 1 frame can be read. data is output as 16 bits divided into 8 upper bits and 8 lower bits. the cc flag must be checked when reading peak level data.
preliminary product information s14470ej1v1pm00 47 m m m m pd63711 (4) f5h command (q code consecutive readout (excluding peak level data)) 11110101 msb command lsb [functional description] use this command to read out consecutive q code data starting from the address specified in the f2h command (incrementing the pointer). refer to the f2h command for the relationship between the address pointer and q code data. when a command other than the f2h, f5h, or f8h commands is input to the m pd63711, the address pointer is initialized (put in the same state as after a reset) automatically to ah (refer to the f2h command). after reading data, the pointer address is incremented ( ? 9 ? a ? 0 ? 1 ? 2 ? ...). the basic reading method is described first. this actually is used in combination with the method of reading n bytes of q code data (described later). ? to read out 1 byte of q code data, use the f2h command. ? to read out multiple bytes of q code data consecutively, read out according to the flowchart shown below. figure 3-2. q code consecutive readout method start input readout command specifying q code address (f2h) input parameter (q code address pointer) readout q code byte data indicated by pointer increment q code address pointer q code consecutive readout command (f5h) input? end yes no
preliminary product information s14470ej1v1pm00 48 m m m m pd63711 a flowchart for actually reading out n bytes of q code data (read out n bytes starting from arbitrary position in a frame) is shown below. figure 3-3. readout method of n bytes of q code data start readout ect and store frame counter readout ect is frame counter the same before and after reading? end is error counter a? read error no yes yes no readout n bytes ; set ??in accordance with the system. ; use 1-byte readout or consecutive readout.
preliminary product information s14470ej1v1pm00 49 m m m m pd63711 (5) f6h command (lrck pin and emph pin polarity switching) 11110110 msb command lsb 0 0 0 0 psel 0 lp ep msb parameter lsb ep emph pin polarity 0 * normal output 1 inverted output lp lrck pin polarity 0 * normal output 1 inverted output psel hold/mirr pin output 1 wdck/wfck signal output 0 * normal output (hold/mirr output) remark the mark * indicates the contents set after a reset. [functional description] ep: selects whether emph pin output is normal or inverted. lp: selects whether lrck pin output is normal or inverted. psel: controls wdck/wfck signal output from hold/mirr pin. caution when using the on-chip d/a converter, be sure to set lp = ep = 0.
preliminary product information s14470ej1v1pm00 50 m m m m pd63711 (6) f7h command (sound output mode and sync window width setting) 11110111 msb command lsb pwm 0 0 0 wd2 wd1 mon at2 msb parameter lsb at2 attenuation (set the attenuation value independently for l and r) 0 * attenuation off 1 attenuation on mon audio output signal switching 0 * normal (stereo) 1 monaural wd2 sync window block 0* 7 plck 0 30 plck wd1 0 1 1 60 plck 0 1 80 plck 1 pwm sound dac pwm off 0 pwm on 1 * pwm off remark the mark * indicates the contents set after a reset. [functional description] at2: selects on or off for attenuation. this is m pd63703 equivalent attenuation. set the amount of l-ch and r-ch attenuation using the fah and fbh commands, respectively. mon: selects stereo or monaural for the audio output signal. wd[2:1]: sets the width of the pll synchronization detection window. pwm: selects on or off for sound dac pwm output. in the default state (pwm off), pwm output (l+, lC, r+, rC) is fixed (+pin: h, Cpin: l). (7) f8h command (nop command) 11111000 msb command lsb [functional description] this command has no object.
preliminary product information s14470ej1v1pm00 51 m m m m pd63711 (8) fah and fbh commands (l-ch and r-ch attenuation amount setting) 11111010 msb command lsb l7 l6 l5 l4 l3 l2 l1 l0 msb parameter lsb l[7:0] l-ch attenuation amount 00000000 - 00000001 - 48 db 00000010 - 42.1 db ~ 11111111 - 0.03 db 11111011 msb command lsb r7 r6 r5 r4 r3 r2 r1 r0 msb parameter lsb r[7:0] r-ch attenuation amount 00000000 - 00000001 - 48 db 00000010 - 42.1 db ~ 11111111 - 0.03 db [functional description] l[7:0] : sets the l-ch attenuation amount. r[7:0]: sets the r-ch attenuation amount. this is m pd63703 equivalent attenuation. as in the case of the m pd63703, this is undefined just after a reset. therefore, after setting the attenuation amount using the fah and fbh commands, execute attenuation with the f7h command.
preliminary product information s14470ej1v1pm00 52 m m m m pd63711 (9) fch command (parameter setting) 11111100 msb command lsb tx br bl t1 t0 s e1 e0 msb parameter lsb s subcode synchronization guard 0 * off 1 on e1 error correction 0 * 2-symbol correction 1 2-symbol correction (if uncorrectable, set c2 flag) e0 0 0 0 triple correction note 1 1 quadruple correction note 1 note can be used only in cd-rom mode. tn = 5 ms t1 forcible muting time 0 * tn 2 0 tn 4 t0 0 1 1 tn 8 0 1 tn 16 1 br bilingual mode 0 * normal output 0 l channel bl 0 1 1 r channel 0 1 l and r reversed 1 tx digital audio interface 0 on 1 * off remark the mark * indicates the contents set after a reset. [functional description] e[1:0]: selects the error correcting capability. s: selects on or off for subcode synchronization guard. t[1:0]: selects the forcible muting time. br, bl: selects the bilingual mode. tx: selects on or off for digital audio interface data output.
preliminary product information s14470ej1v1pm00 53 m m m m pd63711 (10) fdh command (c bit setting) 11111101 msb command lsb s3 s2 s1 s0 0 0 c1 c0 msb parameter lsb c1 clock precision 0 * standard mode level ii 0 variable pitch mode level iii c0 0 1 1 high precision mode level i 0 1 setting prohibited 1 s3 0 * 1 1 0 s2 s1 source number 00 00 10 setting prohibited 2 s0 0 0 0 1 15 1 10 11 0 1 ~ 3 remark the mark * indicates the contents set after a reset. [functional description] c[1:0]: sets the clock precision of the c bit of the digital audio interface. s[3:0]: sets the source number of the c bit of the digital audio interface. this command is only used to output values set for digital audio interface output and is unrelated to other operations of the lsi. (11) feh command (digital attenuation amount setting) 11111110 msb command lsb 000000a1a0 msb parameter lsb a1 attenuation amount 0 C6 db 0 * C12 db a0 0 1 1 C18 db 0 1 C24 db 1 remark the mark * indicates the contents set after a reset. [functional description] a[1:0]: sets the digital attenuation amount.
preliminary product information s14470ej1v1pm00 54 m m m m pd63711 3.4 cd-text function (1) parameter format inputs the parameters at the tsi pin in the format shown below. command input is not necessary. m1 m0 sz a4 a3 a2 a1 a0 msb parameter lsb sz readout data output format selection 0 6/8 conversion 1 none (output 6-bit data justified on the lsb side) a[4:0] readout data address m1 cd-text data processing method 0 interleave autocheck decode mode 0 specifies mode = 4 (lead in area) m0 0 1 1 no interleave decoding 0 1 interleave decoding command 1 mode 2 4 2 2 remark the mark * indicates the contents set after a reset. [functional description] a[4:0]: specifies the readout data address within pack. if sz = 0, specify an address from 0h to 11h. if sz = 1, specify an address from 0h to 17h. if a[4:0] = 18h, output correction results information. sz: selects 6/8 conversion of readout data. 0 there is 6/8 conversion. 1 there is no 6/8 conversion. use sz = 0 as needed to read a mode = 2 (program area) data area. in other cases, use sz = 1. m[1:0]: sets the decoding mode. if m1 = 1, specify the interleave mode in the m0 bit. 00 determines the presence of interleaving in a program area using item of 3 bits and performs automatic de-interleaving. 01 specifies mode = 4 (lead in area). only crc checking is performed and not correction. 10 no de-interleaving 11 has de-interleaving
preliminary product information s14470ej1v1pm00 55 m m m m pd63711 (2) correction result information when a[4:0] = 18h, the following correction result information is output. crc q1 q0 p1 p0 msb lsb p1 error correction state in mode = 2 0 no errors 0 1 error p0 0 1 1 2 errors 0 1 uncorrectable error 1 q1 error correction state in mode = 2 0 no errors 0 1 error q0 0 1 1 2 errors 0 1 uncorrectable error 1 crc result of crc checking in mode = 4 0 crc error 1 crc ok [functional description] p[1:0]: shows the p series error correction state for mode = 2. q[1:0]: shows the q series error correction state for mode = 2. crc: shows the results of crc checking for mode = 4. crc = 1 means crc checking was ok. refer to the crc bit for mode = 4 and the q[1:0] and p[1:0] bits for mode = 2 as needed. figure 3-4. data storage ram address map image (mode = 2) when sz = 1 q1 q2 p1 p2 p3 p4 data field when sz = 0 data field 04h 13h 18h 18h 03h 0eh 11h (correction results information) compression instruction byte item bit
preliminary product information s14470ej1v1pm00 56 m m m m pd63711 (3) 6/8 conversion in mode = 2 (program area), a constituent unit of data is 6 bits. if 8-bit mode is specified at this time, data output from the tso pin is 6-bit data justified on the lsb side (the upper section of figure 3-5). if 6/8 conversion is specified, the 6-bit units of data are compressed and output (the lower section of figure 3-5). therefore, the time needed to read the data is shortened. figure 3-5. data compression in 6/8 conversion 6-bit mode 4567 8-bit mode 345 in 6/8 conversion based on sz = 0, all data except 18h in the ram is compressed. if you wish to read out the item bit using a microcontroller and judge the possession of interleaving, specifying sz = 1 is recommended.
preliminary product information s14470ej1v1pm00 57 m m m m pd63711 3.5 status the status flags can be used to find out the internal state of the lsi. cc psw fr pw msb status lsb pw detection of maximum interval between efm signal transition points 0 maximum interval between efm signal transition points < 188t 1 maximum interval between efm signal transition points 3 188t fr synchronization detection state 0 asynchronized state 1 synchronized state t = bit rate = approximately 231.4 ns pick inner detection cc command execution state 0 command execution finished 1 command execution in progress psw [functional description] pw: this is the maximum value of the inversion interval of the efm signal detected during the rfck period (peak hold) compared to 188t (approximately 43.5 m s). this flag is used to check whether or not rotation stopped when a brake was applied to the spindle for stopping the rotation of a disc. to avoid detection of errors due to defect (etc.), judge rotation to have stopped as long as pw = 1 multiple times in succession. depending on the state of the efm signal, pw may remain equal to 0 if the focus servo is out of position, so in addition to checking the pw flag, also check the focus servo state. fr: in the efm demodulation block, whether the output of the internal frame counter matches with the frame synchronization signal is sampled every wfck/16 and a signal indicating a match or a non-match is output. if this signal indicates non-match 8 times in succession, this is regarded as an asynchronized state (fr = 0). at times other than this, it is regarded as a synchronized state (fr = 1). this flag is used to detect the mirror state of a disc and can be used in a sled servo or spindle servo guard. in addition, clv adaptive servo mode switches the lead-in servo and normal servo according to this flag. psw: outputs the state of the limit pin (pin 39). cc: when cc = 1, the processing of a command input from a microcontroller is being performed. the period in which cc = 1 is at most 12 m s (peak level data readout time).
preliminary product information s14470ej1v1pm00 58 m m m m pd63711 4. package drawing 100 pin plastic lqfp (fine pitch) (14 14) item millimeters inches note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. s100gc-50-8eu f 1.00 0.039 b 14.00 0.20 0.551 +0.009 ?.008 s 1.60 max. 0.063 max. l 0.50 0.20 0.020 +0.008 ?.009 +0.009 ?.008 c 14.00 0.20 0.551 +0.009 ?.008 a 16.00 0.20 0.630 0.008 g 1.00 0.039 h 0.22 0.009 0.002 i 0.08 0.003 j 0.50 (t.p.) 0.020 (t.p.) k 1.00 0.20 0.039 +0.009 ?.008 n 0.08 0.003 p 1.40 0.05 0.055 0.002 r3 3 +7 ? +7 ? d 16.00 0.20 0.630 0.008 m q r k m l j h i f g p n detail of lead end m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 q 0.10 0.05 0.004 0.002 +0.05 ?.04 1 25 26 50 100 76 75 51 cd s a b
preliminary product information s14470ej1v1pm00 59 m m m m pd63711 5. recommended soldering conditions the m pd63711 should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 5-1. surface mounting type soldering conditions m m m m pd63711gc-8eu: 100-pin plastic lqfp (fine pitch) (14 14 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 sec. max. (at 210c or higher), count: two times or less, exposure limit: 3 days note (after that, prebake at 125c for 10 hours) ir35-103-2 vps package peak temperature: 215c, time: 40 sec. max. (at 200c or higher), count: two times or less vp15-00-2 wave soldering solder bath temperature: 260c max., time: 10 sec. max., count: once, preheating temperature: 120c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 300c max., time: 3 sec. max. (per pin row) - note after opening the dry pack, store it at 25c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating).
preliminary product information s14470ej1v1pm00 60 m m m m pd63711 [memo]
preliminary product information s14470ej1v1pm00 61 m m m m pd63711 [memo]
preliminary product information s14470ej1v1pm00 62 m m m m pd63711 [memo]
preliminary product information s14470ej1v1pm00 63 m m m m pd63711 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m m m m pd63711 the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5 98. 8

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